`timescale  1ns/1ns       
module Can_Top( 
                   iClk ,                   
                   iRst_n   ,                       
                   i_mpc_intr_n   ,                                                                   
                   i_miso      ,                                                       			   
                   o_sck       ,                      
                   o_mosi      ,                      
                   o_ssn       ,
                   i_mpc_intr_n_2   ,                                                                    
                   i_miso_2      ,                                                               			   
                   o_sck_2       ,                      
                   o_mosi_2      ,                      
                   o_ssn_2       ,
                   i_mpc_intr_n_3   ,                                                                    
                   i_miso_3      ,                                                              			   
                   o_sck_3       ,                      
                   o_mosi_3      ,                      
                   o_ssn_3       ,
                   i_mpc_intr_n_4   ,                                                                    
                   i_miso_4      ,                                                               			   
                   o_sck_4       ,                      
                   o_mosi_4      ,                      
                   o_ssn_4       ,   
                   ovLED         ,
                   clk_25test
				   );  

//******************Parameter********************//
parameter 		DATA_W = 16;//
//input ports 
input           iClk ;                                                  
input           iRst_n     ;  
//CAN
input           i_mpc_intr_n;  //对端发缓冲为空，接缓冲已满，产生中断                                                                                                                                                                                                    
input           i_miso;                                                                                                                                                                                                                                                         
output          o_sck  ;                  
output          o_mosi ;                 
output          o_ssn  ;
input           i_mpc_intr_n_2;  //对端发缓冲为空，接缓冲已满，产生中断                                                                                                                                                                                                   
input           i_miso_2;                                                                                                                                                                                                                                                        
output          o_sck_2  ;                  
output          o_mosi_2 ;                 
output          o_ssn_2  ;  
input           i_mpc_intr_n_3;  //对端发缓冲为空，接缓冲已满，产生中断                                                                                                                                                                                                   
input           i_miso_3;                                                                                                                                                                                                                                                          
output          o_sck_3  ;                  
output          o_mosi_3 ;                 
output          o_ssn_3  ;  
input           i_mpc_intr_n_4;  //对端发缓冲为空，接缓冲已满，产生中断                                                                                                                                                                                                   
input           i_miso_4;                                                                                                                                                                                                                                                   
output          o_sck_4  ;                  
output          o_mosi_4 ;                 
output          o_ssn_4  ;  
//LED
output [9:0]    ovLED;     
//TEST
output clk_25test; 

//******************CAN********************//
wire      [63:0]        wvCanData_receive1  ; 
wire      [63:0]        wvCanData_receive2  ;
wire      [63:0]        wvCanData_receive3  ; 
wire      [63:0]        wvCanData_receive4  ;


wire      [63:0]        wvCanData_send1;
wire      [63:0]        wvCanData_send2;
wire      [63:0]        wvCanData_send3;
wire      [63:0]        wvCanData_send4;

//******************pack********************//
wire			[15:0]			wvBSC_Key_1;
wire			[15:0]			wvBSC_Wheel1_1;
wire			[15:0]			wvBSC_Wheel2_1;
wire			[15:0]			wvBSC_Wheel3_1;
wire			[31:0]			wvBSC_VERSION_1;
wire			[15:0]			wvBSC_Key_2;
wire			[15:0]			wvBSC_Wheel1_2;
wire			[15:0]			wvBSC_Wheel2_2;
wire			[15:0]			wvBSC_Wheel3_2;
wire			[31:0]			wvBSC_VERSION_2;
		
wire			[15:0]			wvHHC_Key_1;
wire			[15:0]			wvHHC_Wheel1_1;
wire			[15:0]			wvHHC_Wheel2_1;
wire			[15:0]			wvHHC_Wheel3_1;
wire			[31:0]			wvHHC_VERSION_1;
wire			[15:0]			wvHHC_Key_2;
wire			[15:0]			wvHHC_Wheel1_2;
wire			[15:0]			wvHHC_Wheel2_2;
wire			[15:0]			wvHHC_Wheel3_2;
wire			[31:0]			wvHHC_VERSION_2;
wire            [15:0]          wvHBC_LinkState;

//******************Unpack********************//
wire		[15:0]		wvBSC_LED_1;		
wire		[15:0]		wvBSC_LED_2;	
wire		[15:0]		wvHHC_Gantry_1;
wire		[15:0]		wvHHC_Collimator_1;		
wire		[15:0]		wvHHC_Swing_1;		
wire		[15:0]		wvHHC_MLCX1_1;		
wire		[15:0]		wvHHC_MLCX2_1;		
wire		[15:0]		wvHHC_JawY1_1;		
wire		[15:0]		wvHHC_JawY2_1;	
wire		[15:0]		wvHHC_CouchVRT_1;
wire		[15:0]		wvHHC_CouchLAT_1;	
wire		[15:0]		wvHHC_CouchLNG_1;
wire		[15:0]		wvHHC_CouchLED1_1;
wire		[15:0]		wvHHC_CouchLED2_1;
wire		[15:0]		wvHHC_DisplayState_1;
wire		[15:0]		wvHHC_CouchLNGPLAN_1;
wire		[15:0]		wvHHC_MLCX_1;	
wire		[15:0]		wvHHC_MLCY_1;	
wire		[15:0]		wvHHC_Gantry_2;
wire		[15:0]		wvHHC_Collimator_2;		
wire		[15:0]		wvHHC_Swing_2;		
wire		[15:0]		wvHHC_MLCX1_2;		
wire		[15:0]		wvHHC_MLCX2_2;		
wire		[15:0]		wvHHC_JawY1_2;		
wire		[15:0]		wvHHC_JawY2_2;	
wire		[15:0]		wvHHC_CouchVRT_2;
wire		[15:0]		wvHHC_CouchLAT_2;	
wire		[15:0]		wvHHC_CouchLNG_2;
wire		[15:0]		wvHHC_CouchLED1_2;
wire		[15:0]		wvHHC_CouchLED2_2;
wire		[15:0]		wvHHC_DisplayState_2;
wire		[15:0]		wvHHC_CouchLNGPLAN_2;
wire		[15:0]		wvHHC_MLCX_2;	
wire		[15:0]		wvHHC_MLCY_2;
//******************虚拟数据********************//
reg         [63:0]      rvCanData1;
reg         [63:0]      rvCanData2;
reg         [63:0]      rvCanData3;
reg         [63:0]      rvCanData4;
reg         [9:0]       rvLED;
reg         [31:0]      rcount_LED;

assign clk_25test=iClk_25;
//******************锁相环********************//
wire                    iClk_25;//锁相环输出时钟
PLL myPLL(
			.inclk0(iClk),   //  refclk.clk
			.areset(~iRst_n),//  reset.reset
			.c0(iClk_25) // outclk0.clk
			);
//******************上电延时********************//
reg [31:0] rvPowerOn_Delay;
reg rRst_n;
always @(posedge iClk_25 or negedge iRst_n) begin
    if (!iRst_n) begin
        rvPowerOn_Delay<=32'd0;
		rRst_n<=1'd0;
        end
    else begin
        if(rvPowerOn_Delay<=32'd250000000-1)begin
			rvPowerOn_Delay<=rvPowerOn_Delay+1;
			rRst_n<=1'd0;end
		else begin
			rvPowerOn_Delay<=rvPowerOn_Delay;
			rRst_n<=1'd1;end
    end     
end
//******************CAN总线代码********************//
Can_BUS u_Can_BUS_1(
    .iClk         (iClk_25         ),
    .iRst_n       (rRst_n       ),
    .i_mpc_intr_n (i_mpc_intr_n ),
    .i_miso       (i_miso       ),
    .o_sck        (o_sck        ),
    .o_mosi       (o_mosi       ),
    .o_ssn        (o_ssn        ),
    .o_can_data   (wvCanData_receive1   ),
    .iM_S_slect(1'b0),//0:主 1：从
    .i_can_data   (rvCanData1   )
);

Can_BUS u_Can_BUS_2(
    .iClk         (iClk_25         ),
    .iRst_n       (rRst_n       ),
    .i_mpc_intr_n (i_mpc_intr_n_2 ),
    .i_miso       (i_miso_2       ),
    .o_sck        (o_sck_2        ),
    .o_mosi       (o_mosi_2       ),
    .o_ssn        (o_ssn_2        ),
    .o_can_data   (wvCanData_receive2   ),
    .iM_S_slect(1'b1),
    .i_can_data   (rvCanData2   )
);

Can_BUS u_Can_BUS_3(
    .iClk         (iClk_25         ),
    .iRst_n       (rRst_n       ),
    .i_mpc_intr_n (i_mpc_intr_n_3 ),
    .i_miso       (i_miso_3       ),
    .o_sck        (o_sck_3        ),
    .o_mosi       (o_mosi_3       ),
    .o_ssn        (o_ssn_3        ),
    .o_can_data   (wvCanData_receive3   ),
    .iM_S_slect   (1'b0),
    .i_can_data   (rvCanData3   )
);

Can_BUS u_Can_BUS_4(
    .iClk         (iClk_25         ),
    .iRst_n       (rRst_n       ),
    .i_mpc_intr_n (i_mpc_intr_n_4 ),
    .i_miso       (i_miso_4       ),
    .o_sck        (o_sck_4        ),
    .o_mosi       (o_mosi_4       ),
    .o_ssn        (o_ssn_4        ),
    .o_can_data   (wvCanData_receive4   ),
    .iM_S_slect   (1'b1),
    .i_can_data   (rvCanData4   )
);

//数据测试
reg [31:0] counterTest;
reg T_1S;
always @(posedge iClk_25 or negedge rRst_n) begin
    if (!rRst_n) begin
        counterTest<=32'd0;
        T_1S<=1'd0;
        end
    else if(counterTest>=32'd2500000-1) begin
        counterTest<=32'd0;
        T_1S<=1'b1;end
    else begin
        counterTest<=counterTest+32'd1;
        T_1S<=1'b0;end
     
end
always @(posedge iClk_25 or negedge rRst_n) begin
    if (!rRst_n) begin
        rvCanData1<=64'd0;
        rvCanData2<=64'd1000;
        rvCanData3<=64'd2000;
        rvCanData4<=64'd3000;
        end
    else begin
        rvCanData1<=T_1S ? rvCanData1+1 : rvCanData1;
        rvCanData2<=T_1S ? rvCanData2+1 : rvCanData2;
        rvCanData3<=T_1S ? rvCanData3+1 : rvCanData3;
        rvCanData4<=T_1S ? rvCanData4+1 : rvCanData4;
    end     
end
//******************LED测试********************//
assign ovLED=rvLED;
always @(posedge iClk_25 or negedge rRst_n) begin
    if (!rRst_n) begin
        rcount_LED<=32'd0;
        rvLED<=9'd1;
        end
    else begin
        if (rcount_LED<2500000) begin
            rcount_LED<=rcount_LED+1;
			end
        else begin
            rvLED<={rvLED[8:0],rvLED[9]};
            rcount_LED<=32'd0;
			end
    end     
end

endmodule
